· , Publications · , "Chameleon Cache: Approximating Fully Associative Caches with Random Replacement to Prevent Contention-Based Cache Attacks"
· , "Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware." · , Morpheus II accepted to HOST'21 · , Blogs · , "Software-driven Security Attacks: From Vulnerability Sources to Durable Hardware Defenses"
· , · , "Cyclone: Detecting Contention-Based Cache Information Leaks Through Cyclic Interference" · , Our work Cyclone accepted to MICRO'19 · , "Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defenses with Churn" · , Morpheus accepted to ASPLOS'19
· , On the GhostRider FPGA Prototype
· , Projects · , Managing Capabilities in Multi-Processor Systems · , Contention Counters · , "GhostRider: A Hardware-Software System for Memory Trace Oblivious Computation" · , Reducing DRAM Bank Conflicts Through Dynamic Bank Remapping
· , Removing Information Leakage from Branch Predictors
· , Detecting a Virtualized Environment with Performance Counters · , Code Generation for Block-Structured ISA · , ARM Out-of-Order Processor Design
Links to all the blog entires on this site since 2002.
I am currently a graduate student working on a Ph.D. in Electrical & Computer Engineering in the SPARK Research Lab. I am supervised by Professor Mohit Tiwari.