Blogs

Mon, Aug 2, 2021

Morpheus II accepted to HOST'21

Our work on Morpheus II, a RISC-V secure processor deployed on AWS F1 FPGAs, has been accepted to HOST'21! Morpheus II was part of the first DARPA bug bounty FETT where hundreds of security researchers found zero vulnerabilties. Building upon Morpheus (ASPLOS19), our system utilizes run-time encryption of code and code pointers to thwart attacks.

Sat, Jul 20, 2019

Our work Cyclone accepted to MICRO'19

Our work on detecting side-and-covert channels in privacy-sensitive applications has been accepted to MICRO'19!

Sun, Mar 10, 2019

Morpheus accepted to ASPLOS'19

Our joint work with Todd Austin's group at the University of Michigan has been accepted to ASPLOS'19!

Wed, Mar 9, 2016

On the GhostRider FPGA Prototype

In the GhostRider paper, we presented a memory trace oblivious system including a type-system, compiler, ISA additions, and hardware FPGA implementation. GhostRider leverages compiler and microarchitecture co-design to improve upon past systems such as Ascend and Phantom that protect against attackers snooping the off-chip DRAM address bus. By exposing on-chip scratchpads at the ISA-level, the GhostRider compiler is able to control when off-chip accesses occur, preventing timing side channels. Similarly, direct control of the placement of data in Oblivious RAM (ORAM) or Encrypted RAM (ERAM) based on static analysis of the program's access pattern allows for improved performance with the same security guarantee as placing all data in ORAM.