At the 2nd RISC-V workshop in Berkeley, CA I presented a poster on Contention Counters. I modified the Rocket processor to support performance counters that directly measured contention with another thread. As shown in the poster, these counters can be used to easily detect an eavesdropper on contention-based covert channels. Poster (PDF)
For Dr. Tiwari’s Security: Hardware-Software Interface course, Stephen Pruett and I investigated how to prevent side and covert channels in branch predictors. We discovered that static partitioning between concurrent hardware threads (i.e. SMT), combined with predictor state flushing between context switches completely eliminates information leakage at a minimal performance impact. This is unsurprising because typical commercial machines support only a small number of SMT threads, 2 in the case of Intel and 8 in the case of IBM Power8.
Various projects from courses and research.