Morpheus II accepted to HOST'21

2 August 2021

Our work on Morpheus II, a RISC-V secure processor deployed on AWS F1 FPGAs, has been accepted to HOST'21! Morpheus II was part of the first DARPA bug bounty FETT where hundreds of security researchers found zero vulnerabilties. Building upon Morpheus (ASPLOS19), our system utilizes run-time encryption of code and code pointers to thwart attacks.

Our work Cyclone accepted to MICRO'19

20 July 2019

Our work on detecting side-and-covert channels in privacy-sensitive applications has been accepted to MICRO'19!




Morpheus accepted to ASPLOS'19

10 March 2019

Our joint work with Todd Austin's group at the University of Michigan has been accepted to ASPLOS'19!




On the GhostRider FPGA Prototype

9 March 2016

In the GhostRider paper, we presented a memory trace oblivious system including a type-system, compiler, ISA additions, and hardware FPGA implementation. GhostRider leverages compiler and microarchitecture co-design to improve upon past systems such as Ascend and Phantom that protect against attackers snooping the off-chip DRAM address bus. By exposing on-chip scratchpads at the ISA-level, the GhostRider compiler is able to control when off-chip accesses occur, preventing timing side channels. Similarly, direct control of the placement of data in Oblivious RAM (ORAM) or Encrypted RAM (ERAM) based on static analysis of the program's access pattern allows for improved performance with the same security guarantee as placing all data in ORAM.

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Recent Work

  • "Chameleon Cache: Approximating Fully Associative Caches with Random Replacement to Prevent Contention-Based Cache Attacks" Thomas Unterluggauer, Austin Harris, Scott Constable, Fangfei Liu, Carlos Rozas in Proceedings of the 2nd IEEE International Symposium on Secure and Private Execution Environment Design(SEED). Abstract  pdf
  • "Morpheus II: A RISC-V Security Extension for Protecting Vulnerable Software and Hardware" Austin Harris, Tarunesh Verma, Shijia Wei, Alex Kisil, Misiker Tadesse Aga, Valeria Bertacco, Baris Kasikci, Mohit Tiwari, Todd Austin,in Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust(HOST). Abstract  pdf
  • "Software-driven Security Attacks: From Vulnerability Sources to Durable Hardware Defenses" Lauren Biernacki, Mark Gallagher, Zhixing Xu, Misiker Tadesse Aga, Austin Harris, Shijia Wei, Mohit Tiwari, Baris Kasikci, Sharad Malik, Todd Austin, in Proceedings of the ACM Journal on Emerging Technologies in Computing Systems(JETC). Abstract  pdf
  • "Cyclone: Detecting Contention-Based Cache Information Leaks Through Cyclic Interference" Austin Harris, Shijia Wei, Prateek Sahu, Pranav Kumar, Mohit Tiwari, Todd Austin, in Proceedings of the 52nd International Symposium on Microarchitecture (MICRO). Abstract  pdf
  • "Morpheus: A Vulnerability-Tolerant Secure Architecture Based on Ensembles of Moving Target Defenses with Churn" Mark Gallagher, Lauren Biernacki, Shibo Chen, Zelalem Birhanu Aweke, Salessawi Ferede Yitbarek, Misiker Tadesse Aga, Austin Harris, Zhixing Xu, Baris Kasikci, Valeria Bertacco, Sharad Malik, Mohit Tiwari, Todd Austin, in Proceedings of the 24th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). Abstract  pdf

about

I am currently a graduate student working on a Ph.D. in Electrical & Computer Engineering in the SPARK Research Lab. I am supervised by Professor Mohit Tiwari.

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